Minecraft logic – 4 bit, 4 bank asynchronous RAM array
This is a memory array I’ve built in minecraft over the past couple days – the design is an asynchronous (unclocked) 4 bit wide memory array consisting of 4 banks. The total data storage is only 16 bits, but the data can be accessed in any order and written at will without manually flipping switches inside each cell. The design is also easily extensible, and should continue to operate well to at least 4x the dimensions in each direction, for a total array size of 256 bits or so (if you had enough patience to assemble it!). The circuit is designed to be asynchronous, but lacks a couple external interface elements (data_ready, etc…) to make it a fully asynchronous design that could be paired with other logical blocks. These would be easy to implement, and I’ve just left them out because they serve no purpose in a stand-alone test array like this. Each cell is 10×12 blocks of area including space between cells, and occupies 4 blocks of height including floors for the logic itself, with an additional floor above and below for data and control lines. The cells themselves switch in about 300-500ms, and the data lines take just under 2 seconds to propagate around the whole loop (this could be reduced at least 30% with some more clever design tricks). A flow-in flow-out memory design (where the array’s data output is on the opposite side from the input) would cut that reduced value in half again or so. There are a few tricks to minimize cell area in use, but you might be able …
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I have no idea what you are talking about but it like it
(i do know about logic gates though
)
what is this I don’t even…
@snigefar
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did Centy tried to understand redstone wiring ?
also its actually holding 32-bits of memory with the two chips chips have done.
im building a memory bank using a compact D-flip flop system, this allows for more compact data management and is capable of saving to the main video drive,loading from a network thats like the internet but only limited to single player,
auto skipping to the next memory chip if one is full, notfying you if all the chips are full and playing GS-Video (Gray Scale-video) it it has a reading and writing system using 1-bit, 2-bit, 4-, and 16-bit combination system im including it in the cpu im making
@tucense Yes I comment a lot.
@tucense That would occupy 7,500 blocks. If its 4 banks of 8 bytes that is 32 bytes or 256 bits. So one bit would occupy ~30 blocks. That is like 2x3x5. I very much doubt you have a entire bit including all its connections (D, C, E, Q) in just a 2x3x5 area. Now if you meant 8 bytes spread out over 4 banks then that’s not very compact at all. That’s ~937 blocks for each bit (similar to 4x5x47) which is bigger then the first bit I ever made, and that thing was insanely big. Go measure it again.
@ixcaliber I made a 4 bank 8 byte of this in 20W 25L 15H, You can definetly compact these things down. I wish there was an easy way to show people schematics.
@ixcaliber HI… I swear I see your name on every video.. lol
yaaa. i do that when i get it :S
@deathandmp5 What if you did the 32-bit ALU or whatever?
Bitch below me gives computer viruses don’t do it
like a premium minecraft account? type MYPRIZE as opposed to YOU in youtube and then press enter
How did you read each individual bank when you select them.
@MinecraftingDaddio Nvm.
Isnt it an RS NOR Latch?
THIS, IS, CONFUSING!!!!! (angry spartan voice)
Um would it be a possibility for you to make a vid on how you linked all of these individual cells together?
@siberx4 Well a ROM would work if I built a simple program or permanent info. But for my purposes, I need to be able to write and change it efficiently. My goal is to create a 64byte RAM with 2 address buses and make the entire thing only 112x86x8 (including everything), but my bit designs always have one really annoying issue that ends up taking like 5 blocks to fix and the rerouting of some other wire, making it pointless. I will keep working at it though.
@ixcaliber And welcome to the problem every early real-world integrated circuit designer faced; memory takes up a lot of freakin’ space!
You can save a lot of space by using read-only memory arrays where you can spare it, and just try and make your design as efficient as possible for memory use. Also, using type-specific memories (like compact RS latches in-place with clever logic around them) instead of relying on a general-purpose array of D-latches can save a lot of space/memory too.
@siberx4 That design on wiki is flawed, but I can probably make my own design. I have some idea in mind for making a 4x2x6 (l x w x h)(including input/output lines) bit. Another problem I made is my Enable and the clock were attached to an AND gate before the C input, which is fine because I don’t want to overwrite it accidentally, but I only need 1 and gate for the entire byte, not for each one. Mine is very fast though, but 8bytes takes 32x20x60 blocks! It’s way too big.
@ixcaliber Your bit should be smaller than that; that’s a volume of 660 blocks! My best design before repeaters were added was roughly 4x9x4 tile-able without the data lines driving it (144 block volume). I saw a very efficient 1-wide blade D-latch design on the wiki (D flip-flop design C, tileable volume of probably 70-100 blocks) that combined with a couple elements could make for a very compact read/write memory cell. Be sure to check the wiki for good compact designs you can modify!
@siberx4 Alright, I use an AND gate, but my bit is massive (15x4x11). I have picked a few things I could simplify (some double not gates), but that AND gate is what makes that 11 so high, it should only be about 6 high if I just wired the output directly to the display.
@ixcaliber Correct – since Minecraft only has driven and undriven states (no driven high and driven low) all it takes to disable an output is to make sure it doesn’t drive a logic 1. An AND tied to the output with an enable high line does this just fine. Nowadays I would probably use a piston-gate instead, as it’s likely more compact in this application.